От: fpga journal update [news@fpgajournal.com]
Отправлено: 7 июля 2004 г. 3:02
Кому: Michael Dolinsky
Тема: FPGA Journal Update Vol IV No 01


a techfocus media publication :: July 6, 2004 :: volume IV, no. 01


FROM THE EDITOR

My daughters’ dog died this week. He was a wonderful fourteen-year-old Collie named “Tucker.” We will all miss him. Fourteen years may not seem like that much, but dogs age faster than humans. “Dog years” pass at a rate of about seven per human year, so Tucker lived to the ripe-old equivalent age of ninety-eight.

FPGA gate counts work a little like that too. Comparing them with ASIC measurements is truly like comparing apples and oranges, and reasonable metrics are basically unobtainable. Sometimes people even refer to them as "Dog Gates." This problem, combined with marketing’s propensity for making their products look good, leads to an understandable level of statistical obfuscation. Our feature farsicle “Terminology Tango 101” makes a futile tongue-in-cheek attempt to unravel the myriad mysteries of FPGA factoidism.

Our second article “DSP for Less” by Gordon Hands of Lattice Semiconductor takes a serious look at the exciting prospect of DSP design with new low-cost FPGAs such as those just announced by Lattice. If DSP design with FPGAs was a good idea before, it’s even more compelling with the huge recent reduction in the price of DSP-ready FPGA hardware.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal

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CURRENT FEATURE ARTICLES

Terminology Tango 101
From Dog Gates to Marketing Megahertz

High-Performance DSP Capability Within an Optimized Low-Cost FPGA Architecture
by Gordon Hands, Strategic Marketing Manager, Lattice Semiconductor Corporation
Ken McElvain
Soul of Synplicity

Low Cost Leapfrog

New FPGAs Jump into the High Volume Arena
Semi-Programmable
New Architectures Optimize the Mix
Xilinx Goes Retro
Moving Ahead by Looking Back
Prototype to Production
Structured ASIC Lowers Cost and Power
by Dave Larson, AMI Semiconductor
DAC's Dangerous Undertones
Winds of Change in EDA
Cool and Groovy at DAC
What's Hot in Design Automation
Virtex-4
Xilinx Details Its Next Generation
Racing for the Gap
Altera and Synopsys go Structured

Terminology Tango 101
From Dog Gates to Marketing Megahertz

Pay attention now, there will be a quiz.

In today’s lesson, we’re going to pick the best FPGA. Well, more accurately, we’re going to learn how to pick the best FPGA. The actual proof will be left as an exercise for the student. Since we’re engineers, we can’t rely on any touchy-feely stuff. It doesn’t matter who has the coolest name. We don’t even care who’s got the slickest icon printed on top of their BGA packages. We need a formula. Once we’ve got the right formula, we can read the data sheets, plug in all the numbers and… voilà! The prince of programmability will leap from the page into our collective consciousness.

To build our formula we’re going to need terms. (Any good formula has them…) Since we always talk about gates, we should definitely have them as one of our terms. Everyone knows that gates are good, and, being good, go on the top of our equation. When the number of gates gets bigger, our “goodness” metric will get bigger.

Another thing that always comes up is cost. Cost is bad. We don’t want too much of it, and less is always better. We’ll slide cost in on the bottom of our equation. Now we’re getting somewhere! We’ve got both a numerator and a denominator and our magic metric is starting to take shape. [more]


High-Performance DSP Capability Within an Optimized Low-Cost FPGA Architecture
by Gordon Hands, Strategic Marketing Manager, Lattice Semiconductor Corporation

The applications of Digital Signal Processing (DSP) continue to expand, driven by trends such as the increased use of video and still images and the demand for increasingly reconfigurable systems such as Software Defined Radio (SDR). Many of these applications combine the need for significant DSP processing with cost sensitivity, creating demand for high-performance, low-cost DSP solutions.

General-purpose DSP chips and FPGAs are two common methods of implementing DSP functions, although, until now, the choice of an FPGA implementation has been limited to high-end, expensive platforms. Each approach has advantages, and the optimum implementation method will vary depending upon application requirements. This article provides an overview of common DSP functions and explores the differences between general purpose DSPs and FPGAs. This is followed by a description of the optimized, low-cost LatticeECP-DSP™ FPGA architecture, and a comparison of the LatticeECP-DSP to existing FPGA solutions. [more]


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